1. Field of the Invention
The present invention relates to a multiple line grid array package (MLGA package) and more particularly, to the multiple line grid array package having a package body with electrical circuit patterns according to specific design rules, on which a semiconductor chip is equipped and input/output nodes for supplying electrical signals to the semiconductor chip are exposed, and multiple line grids which electrically connect the input/output nodes with an external device.
2. Related Art
Generally, a ceramic pin grid array package (PGA) includes a multilayer ceramic structure which is formed by a desired process, and cylindrical metallic lead pins which are attached on the multilayer ceramic structure.
FIGS. 1A to 1C show an example of a conventional ceramic package which has the structure as described above.
As shown in FIG. 1A, there is provided a multilayer ceramic structure (package body 1) which is comprised of, for example, four ceramic layers 1a, 1b, 1c, 1d. Here, a first ceramic layer la located at the very bottom of the four ceramic layers is a dummy layer, and at the center portion of a second ceramic layer 1b is mounted a semiconductor chip 2. First electrode lines 4a are printed around the semiconductor chip 2 on the upper face of the second ceramic layer 1b for transferring electrical signals to each part of the semiconductor chip 2.
A third ceramic layer 1c is provided with a first cavity (not shown) which has a size capable of accommodating the semiconductor chip 2. Second electrode lines 4b are printed around the first cavity on the upper face of the third ceramic layer 1c. A fourth ceramic layer 1d is also provided with a second cavity which has a size capable of accommodating the semiconductor chip 2.
Around the second cavity 3 on the upper face of the fourth ceramic layer 1d, there are a plurality of input/output nodes 6 aligned apart from each other at regular intervals.
In addition, a plurality of via holes (not shown) for electrically connecting the respective input/output nodes 6 with the corresponding first and second electrode lines 4a, 4b are formed in the second, third and fourth ceramic layers 1b, 1c, 1d. The via holes are filled with conductive paste.
In FIG. 1A, there are shown upper portions 5 of the via holes filled with the conductive paste. Therefore, when the electrical signals are transferred to the input/output nodes 6, the electrical signals are continuously transferred through the first and second electrode lines 4a, 4b to terminals in the semiconductor chip 2.
Lead pins 7 for transferring the electrical signals are bonded to the package body 1. The lead pins 7 are typically made of a metal, and are formed into cylindrical pins. Furthermore, each of the lead pins 7 is connected with each of the corresponding input/output nodes 6.
FIG. 1B is a partially enlarged view of the package body 1 in FIG. 1A. The lead pins 7 are bonded to the corresponding input/output nodes 6 by brazing 7a. 
FIG. 1C is a cross-sectional view along the line C-Cxe2x80x2 of FIG. 1B. The plurality of via holes are formed in the package body 1, and the via holes are filled with the conductive paste T. The respective ceramic layers 1a, 1b, 1c, 1d composing the package body 1 are provided with the first and second electrode lines 4a, 4b which are printed on the upper face of the ceramic layers 1a, 1b, 1c, 1d. The ceramic layers 1a, 1b, 1c, 1d are laminated to each other by pressure, followed by firing at high temperatures.
However, in the conventional pin grid array package as mentioned above, there are some problems as follows:
First, since the lead pins 7 are respectively connected with the corresponding input/output nodes 6 on the upper face of the ceramic package body 1, it is required that the number of the lead pins 7 should be as many in number as the input/output nodes 6. Therefore, as the integration density of the semiconductor chip increases, the number of the input/output nodes 6 likewise increases.
Such increase in the number of nodes and pins in the semiconductor chip causes the manufacturing cost of the ceramic package to increase, and the size of the package is also increased.
It is therefore an object of the present invention to provide a multiple line grid array package in which the manufacturing cost and the size thereof can be decreased.
One of the above objects which will be apparent to one skilled in the art upon a reading of this disclosure are attained by:
A multiple line grid array package comprising a package body on which a semiconductor chip is mounted and input/output nodes for supplying a electrical signal to the semiconductor chip are exposed, a multiple line grid for electrically connecting the input/output nodes of the package body with an external device is characterized in that a number of conductors are formed parallel to an axis on the outer side or interior of the multiple line grid, and that the conductors are bonded to the respective unit input/output nodes corresponding to each other.
The package body has electrical circuit patterns and includes a nonconductive substrate such as a polymer, a ceramic, or a polymer-ceramic composite, a number of wire bond pads, input/output nodes and electrode lines. If necessary, the package body further includes via hole pads. A number of electrode lines may be located between the multiple line grid and the adjacent multiple line grid on the upper surface of the package body. Alternatively, no electrode line may be located between the two adjacent multiple line grids. The via hole pads may also be located in the inside and/or outside of the areas where the multiple line grids are to be attached. The input/output node has various shapes and various sizes depending on the shape and size of the multiple line grid.
The multiple line grid made of a conductive material and a nonconductive material may be formed into one of a rectangular disc, a circular disc, a cylindrical shape, and elliptical cylinder and a hexahedron, etc., and the height of the multiple line grid is formed to be longer or shorter than its width.
According to the present invention, one multiple line grid can be connected with a number of the input/output nodes, whereby the number of lead pins can be reduced considerably.
In addition, according to the pattern of the present invention, a number of the input/output nodes are arranged within small area and the signal delivery delay is prevented due to the reduction of the length of the electrode lines.